1. Field of the Invention
The present invention relates to the field of integrated circuit memory devices, such as flash memory, and more particularly to memory devices in which the memory array has an endurance specified according to a number of program and erase cycles that the memory cell can endure within a performance tolerance, and for utilizing the memory array for a greater number of cycles than that specified.
2. Description of Related Art
Integrated circuit memory devices are typically used in computer systems or other data processing systems in which there is a subset of data that is changed more often than other data stored in the memory. For example, in data processing systems which rely on sensors to provide input data, the data structure in which the sensor data is stored is updated with new sensor data more often than instructions for programs. Thus, those subsets of the memory which are used to store data structures that change often tend to fail due to the effects of the large number of change cycles that they endure.
Some integrated circuit memory architectures, such as flash memory based on floating gate memory cells, have a relatively low endurance compared to other technologies. However, the flash memory provides a non-volatile memory store which is necessary for some environments. The use of flash memory in environments requiring high endurance memory is limited by the native endurance of the memory cells on the device.
Thus, there is a need for a technique to allow utilization of a non-volatile memory devices in high change cycle environments.
The present invention provides a method for increasing endurance of an array of memory cells which have an endurance specified according to the number of change cycles that the memory cell can endure within a performance tolerance. For example, for an array of flash memory devices, floating gate memory cells in the flash memory device have an endurance specified of for example 10,000 program/erase cycles that the memory cell can safely endure. Beyond the specified number, the cell degrades, and suffers charge gain or loss caused by damage to the tunnel oxide in the cell or other damage of the memory cell.
The method is based on arranging the array into a plurality of sectors, and assigning a subset of addresses for storage of data expected to change a number of times that is sufficient to exceed the specified endurance of the memory cell in the array. According to the method, a record is maintained indicating one of the plurality of sectors as a current sector, directing accesses using the subset of addresses to the current sector, counting changes executed to memory cells identified by the subset of addresses for the current sector, and changing the current sector to another one of the plurality of sectors when the count of changes exceeds the threshold. In this way, a data structure that must be updated many times can be stored in a non-volatile memory device having limited endurance, by taking advantage of the areas in the memory array which store data that is not subject to as many change cycles.
Thus, according to one aspect the plurality of sectors include a particular sector and a number N, where N is at least 1, of substitute sector(s) in the array. The step of changing the current sector includes changing the current sector to one of the particular sector and the N substitute sector(s). The number N is greater than 1, and preferably greater than 5, and for an endurance cycling of 10 times the specified endurance, the number N is greater than or equal to 9.
According to another aspect, the method includes generating a count of erase operations to the current sector, and storing the count in a non-volatile memory store.
According to another aspect of the invention, the array is divided into a first sector, a second sector and a third sector. Other embodiments utilize more than three sectors. Addresses for accessing the array include a first subset of addresses normally assigned to the first sector, a second subset of addresses normally assigned to the second sector, and a third subset of that of addresses normally assigned to the third sector. In this embodiment, the first subset of addresses is assigned to the data structure which is expected to undergo a large number of change cycles. The process of changing the current sector according to this aspect of the invention includes directing accesses using the first subset of addresses to the current sector, accesses using the second subset of addresses to another one of the first, second and third sectors, and accesses using the third subset of addresses to a remaining one of the first, second and third sectors. The current sector is changed to another one of the first, second and third sectors when the count of changes exceeds the threshold. The changing of the current sector includes selecting a next current sector, transferring data stored in the next current sector to the current sector, and redirecting accesses using the first subset of addresses to the next current sector. Furthermore, the method includes redirecting accesses using the one of the second and third subsets of addresses that had been assigned to the next current sector to the current sector, and updating the record of the current sector to indicate the next current sector. When more than three sectors are utilized, the current sector is cycled through more than three sectors, for even greater endurance.
The present invention can also be characterized as an integrated circuit memory including an array of floating gate memory cells, in which memory cells have an endurance specified according to a number of erase cycles that the memory cell can endure within a performance tolerance. The array includes a particular sector and a number N of substitute sectors in the array. Addressing logic is coupled to the array which enables access to memory cells in the array in response to addresses in a range of addresses. The range of addresses includes a subset of addresses for accessing the particular sector in the array. The substitute sectors fall outside the normal range of addresses. Erase cycling logic is coupled to the addressing logic and the array, and maintains a record indicating one of the particular sector and the N substitute sectors as the current sector. The logic directs accesses using the subset of addresses to the current sector, counts the erases executed to memory cells identified by the subset of addresses for the current sector, and changes the current sector another one of the substitute sectors and the particular sector when the count of erases exceeds the threshold.
According to another aspect of the invention it can be characterized as integrated circuit memory in which the addressing logic enables access to memory cells in the array in response to addresses in a range of addresses that includes a first subset of addresses for accessing a first sector in the plurality of sectors, a second subset of addresses for accessing a second sector in the plurality of sectors, and a third subset of addresses for accessing a third sector in the plurality of sectors. Erase cycling logic is coupled to the addressing logic and to the array, which maintains a record indicating one of the first, second and third sectors is a current sector. The logic directs accesses using the first subset of addresses to the current sector, accesses using the second subset of addresses to another one of the first, second and third sectors and accesses using the third subset of addresses to a remaining one of the first, second and third sectors. The logic also counts changes executed in the memory cells identified by the first subset of addresses for the current sector and changes the current sector to another one of the first, second and third sectors when the count of changes exceeds a threshold.
The erase cycling logic which changes the current sector includes logic to select a next current sector to which accesses using one of the second and third subset of addresses are directed, transfers data stored in the next current sector to the current sector, signals the addressing logic to redirect accesses using the first subset of addresses to the next current sector, signals the addressing logic to redirect accesses using one of the second and third subsets of addresses to the current sector, and updates the record of the current sector to indicate the next current sector. Furthermore, the erase cycling logic includes logic which writes data from the current sector to the next current sector prior to signaling the addressing logic to redirect accesses. As mentioned before, more than three sectors can be cycled in this way for greater endurance.
Accordingly, using for example a flash memory technology specified for an endurance of 10,000 program/erase cycles, an endurance of for example 100,000 programs/erase cycles can be achieved for data structures having high change expectations according to the present invention. The present invention provides techniques which solve the problem with a tradeoff of penalty in die size and/or the time consumed in the program and erase cycling.
Other aspects and advantages of the present invention can be seen upon review of the figures, the detailed description and the claims which follow.